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march 2012 ? 2007 fairchild semiconductor corporation www.fairchildsemi.com fssd07 rev. 1.0.2 fssd07 ? 1-bit / 4-bit sd/sdio and mmc dual-host multiplexer fssd07 1-bit / 4-bit sd/sdio and mmc dual-host multiplexer features ? on resistance: 5 ? typical, v ddc =2.7v ? f toggle : >75mhz ? low on capacitance: 6pf typical ? low power consumption: 2a maximum ? supports secure digital (sd), secure digital i/o (sdio), and multimedia card (mmc) specifications ? supports 1-bit / 4-bit host controllers (v ddh1/h2 =1.65v to 3.6v) communicating with high-voltage (2.7-3.6v) and dual-voltage cards (1.65-1.95v, 2.7-3.6v) - v ddc =1.65 to 3.6v, v ddh1/h2 =1.65 to 3.6v ? 24-lead mlp and umlp packages applications ? cell phone, pda, digital camera, portable gps, and notebook computer ? lcd monitor, tv, and set-top box related resources ? fssd07 evaluation board ? evaluation board users guide ? for samples, questions, or board requests; please contact analogswitch@fairchildsemi.com description the fssd07 is a 2:1 multiplexer that allows dual secure digital (sd), secure digital i/o (sdio), and multimedia card (mmc) host controllers to share a common peripheral. the host controllers can be equal to, greater than, or less than peripheral card supply with minimal power consumption. this configuration enables dual host cmd, clk, and d[3:0] si gnals to be multiplexed to a common peripheral. the architecture includes the necessary bi-directional data and command transfer capability for single high- voltage cards or dual-voltage supply cards. the clock path is a uni-directional buffer. typical applications involve switching in portables and consumer applications: cell phones, digital cameras, home theater monitors, se t-top boxes, and notebooks. figure 1. analog symbol diagram ordering information part number top mark operating temperature range package description packing method fssd07bqx fssd07 -40c to +85c 24-lead molded leadless package (mlp), jedec mo-220, 3.5 x 4.5mm tape & reel fssd07umx jk -40c to +85c 24-lead ultra-thin molded leadless package (umlp), 0.4mm pitch tape & reel
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fssd07 rev. 1.0.2 2 fssd07 ? 1-bit / 4-bit sd/sdio and mmc dual-host multiplexer pin configuration 12 11 6 7 8 9 10 15 17 18 19 oe vddc gnd 1 22423 13 14 3 4 5 20 21 22 dat[2] 1cmd 1clk dat[3] clk dat[0] cmd dat[1] 2cmd vddh2 1dat[1] 2dat[2] vddh1 1dat[2] 1dat[3] 1dat[0] 2dat[3] 16 s 2dat[1] 2dat[0] 2clk dat[3] cmd vddc gnd clk 1clk 2cmd dat[0] 1dat[0] 1dat[1] 2dat[3] 2dat[2] s dat[1] 2dat[1] 2dat[0] 2clk vddh2 1 2 3 4 5 6 24 10 9 8 7 14 13 12 11 19 18 17 16 15 23 22 21 20 dat[2] oe 1dat[2] 1dat[3] 1cmd vddh1 figure 2. mlp pin assignments figure 3. umlp pin assignments pin definitions pin# mlp pin# umlp name description 1 22 1dat[2] sdio common port 2 23 oe output enable (active high) 3 24 dat[2] sdio common port 4 1 dat[3] 5 2 cmd 6 3 vddc power supply (sdio peripheral card port) 7 4 gnd ground 8 5 clk clock path port 9 6 dat[0] sdio common port 10 7 dat[1] 11 8 s select pin 12 9 2dat[1] host common port 13 10 2dat[0] 14 11 2clk clock path port 15 12 vddh2 power supply (host port) 16 13 2cmd host common port 17 14 2dat[3] 18 15 2dat[2] 19 16 1dat[1] 20 17 1dat[0] 21 18 1clk clock path port 22 19 vddh1 power supply (sdio host port) 23 20 1cmd host common port 24 21 1dat[3] truth table oe s function high low 1cmd, 1clk, 1dat[3:0] connected to cmd, clk, dat[3:0] high high 2cmd, 2clk,2dat[3:0] connected to cmd, clk, dat[3:0] low x cmd, dat[3:0] ports high impedance; clk is f unction of selected nclk
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fssd07 rev. 1.0.2 3 fssd07 ? 1-bit / 4-bit sd/sdio and mmc dual-host multiplexer typical application figure 4. typical application diagram cmd, dat[3:0] 5 1.65v to 3.6v processor #1 vddc gnd oe s fssd07 clk 1.65v to 3.6v wifi, bluetooth, mmc or sd peripheral vddh1 5 1cmd, 1dat[3:0] 1clk r cmd , r dat[3:0] vddh2 5 2cmd, 2dat[3:0] 2clk secure data/ multi media card dual host selector sd card r 1cmd, 2cmd = 10k to 100k ohm r 1dat[3:0] , 2dat[3:0] = 10k to 100k ohm mmc card r 1cmd, 2cmd = 4.7k to 100k ohm r 1dat[3:0], 2dat[3:0] = 50k to 100k ohm 1.65v to 3.6v processor #2 cmd, dat[3:0] 5 1.65v to 3.6v processor #1 vddc gnd oe s fssd07 clk 1.65v to 3.6v wifi, bluetooth, mmc or sd peripheral vddh1 5 1cmd, 1dat[3:0] 1clk r cmd , r dat[3:0] vddh2 5 2cmd, 2dat[3:0] 2clk secure data/ multi media card dual host selector sd card r 1cmd, 2cmd = 10k to 100k ohm r 1dat[3:0] , 2dat[3:0] = 10k to 100k ohm mmc card r 1cmd, 2cmd = 4.7k to 100k ohm r 1dat[3:0], 2dat[3:0] = 50k to 100k ohm 1.65v to 3.6v processor #2
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fssd07 rev. 1.0.2 4 fssd07 ? 1-bit / 4-bit sd/sdio and mmc dual-host multiplexer functional description the fssd07 enables the multiplexing of dual asic / baseband processor hosts to a common peripheral card or module, providing bi-dir ectional support of the dual- voltage sd/sdio or mmc cards available in the marketplace. each host sdio port has its own supply rail, such that hosts with different supplies can be interfaced to a common peripheral module or card. the peripheral card supply must be equal to or greater than the host(s) to minimize power consumption. the independent v ddc , v ddh1 , and v ddh2 are defined by the supplies connected from the application power management ics (pmics) to the fssd07. the clock path is a uni-directional buffe red path rather than a bi- directional switch port. the supplies (v ddc , v ddh1 , and v ddh2 ) have an internal termination resistor (typically 3m ? ) to ensure the supply rails internally do not float if the application turns off one or all of these sources. cmd, dat bus pull-ups the cmd and dat[3:0] ports do not have, internally, the system pull-up resistors as defined in the mmc or sd card system bus specificat ions. the system bus pull-up must be added external to the fssd07. the value, within the specific specificati on limits, is a function of the individual application and type of card or peripheral connected. for sd card applications, the r cmd and r dat pull-ups should be between 10k ? and 100k ? . for mmc applications, the r cmd pull-ups should be between 4.7k ? and 100k ? , and the r dat pull-ups between 50k ? and 100k ? . the card-side cmd and dat[3:0] outputs have a circuit that facilitates incident wave switching, so the external pull-up resistor s ensure retention of the output high level. the oe pin can be used to place the cmd and dat[3:0] into high-impedance mode during power-up sequencing or when the system enters idle state ( see idle state cmd/dat bus ?parking? ). clk bus the 1clk and 2clk inputs are bi-state buffer architectures, rather than a switch i/o, to ensure 52mhz incident wave switching. si nce most host controllers also have a clock enable register bit to enable or disable the system clock when in id le mode, the clk output is not disabled by the oe pin. instead, the clk output is a function of whichever host cont roller clock is selected by the s pin. consequently, there is alwa ys a clock path connected between the selected host and t he card. the state of the clk pin is a function of the selected host controller nclk output pin, which fac ilitates retaining clock duty cycle in the system or performing read / wait operations. idle state & power-up cmd/dat bus ?parking? the sd and mmc card specifications were written for a direct point-to-point communication between host controller and card. the introduction of the fssd07 in that path, as an expander, r equires that the functional operation and system latenc y not be impacted by the switch characteristics. si nce there are various card formats, protocols, and conf igurable controllers, an oe pin is available to facilitate a fast idle transition for the cmd/dat[3:0] outputs. some controllers, rather than placing cmd/dat into hi gh-impedance mode, pull the outputs high for a clock cycle prior to going into high- impedance mode (referred to as ?parking? the output). some legacy controllers pull their outputs high versus high impedance. if the oe pin is pulled high and the controller places its command and data outputs into high-impedance (driving ncmd/ndat[3:0]), the f ssd07 cmd/dat[3:0] output rise time is a function of the rc time constant through the switch path. pulling oe low puts the switches into high impedance, disabling communication from the host to card, and the cmd/dat[3: 0] outputs are pulled high by the system pull-up re sistors chosen for the application. this mechani sm facilitates power-up sequencing by holding oe lo w until supplies are stable and communication between the host(s) and card is enabled. power optimization since the fssd07 has multiple supplies (v ddc , v ddh1 , and v ddh2 ), the control signals have been referenced to the card peripheral side (v ddc ). to minimize power consumption, current pat hs between supplies are isolated when one or more supplies are not present. this includes the configurat ion of the removal of v ddc with host controller supplies remaining present.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fssd07 rev. 1.0.2 5 fssd07 ? 1-bit / 4-bit sd/sdio and mmc dual-host multiplexer absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the devic e may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stre sses above the recommended operating conditi ons may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter conditions min. max. unit v ddc card supply voltage -0.5 4.6 v v ddh1 ,v ddh2 host controller supply voltage -0.5 4.6 v v sw switch i/o voltage (1) 1dat[3:0], 2dat[3:0], 1cmd, 2cmd pins -0.5 v ddx (2) + 0.3v (4.6v maximum) v dat[3:0], cmd pins -0.5 v ddx (2) + 0.3v (4.6v maximum) v v cntrl control input voltage (1) s, oe -0.5 4.6 v v clki clk input voltage (1) 1clk, 2clk -0.5 4.6 v v clko clk output voltage (1) clk -0.5 v ddx (2) + 0.3v (4.6v maximum) v i indc input clamp diode current -50 ma i sw switch i/o current sdio continuous 50 ma i swpeak peak switch current sdio pulsed at 1ms duration, <10% duty cycle 100 ma t stg storage temperature range -65 +150 ? c t j maximum junction temperature +150 ? c t l lead temperature soldering, 10 seconds +260 ? c esd human body model, jedec: jesd22-a114 i/o to gnd 8 kv supply to gnd 10 all other pins 5 charged device model, jedec-jesd-c101 2 notes: 1. the input and output negativ e ratings may be exceeded if the input and out put diode current ratings are observed. 2. v ddx references the specific sdio port v dd rail (i.e. v ddh1 , v ddh2 , v ddc ). recommended operating conditions the recommended operating conditions table defines the conditions for actual device oper ation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificat ions. fairchild does not recommend exceeding them or designi ng to absolute maximum ratings. symbol parameter min. max. unit v ddc supply voltage - card side 1.65 3.60 v v ddh1, v ddh2 supply voltage - dual host controller 1.65 3.60 v v cntrl control input voltage - v s , v oe 0 v ddc v v clki clock input voltage - v clki 0 v ddh1/h2 v v sw switch i/o voltage cmd, dat[3:0] 0 v ddc v 1cmd, 1dat[3:0] 0 v ddh1 v 2cmd, 2dat[3:0] 0 v ddh2 v t a operating temper ature -40 +85 c ? ja thermal resistance, free air mlp package +50 c/w
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fssd07 rev. 1.0.2 6 fssd07 ? 1-bit / 4-bit sd/sdio and mmc dual-host multiplexer dc electrical characteristics at 1.8v v ddc all typical values are for v ddc =1.8v at 25c unless otherwise specified. symbol parameter v ddc (v) v ddh1 / v ddh2 (v) conditions t a =-40 to +85c unit min. typ. max. common pins v ik clamp diode voltage 1.80 1.80 i ik =-18ma -1.2 v v ih control input voltage high 1.80 1.80 1.3 v v il control input voltage low 1.80 1.80 0.5 v i in s, oe input high current 1.95 1.95 v cntrl =0v to v ddc -1 1 a i oz off leakage, current of all ports 1.95 1.95 v sw =0v to v ddc -1.0 0.5 1.0 a v ohc clk output voltage high (3) 1.95 1.95 i oh =-2ma 1.6 v v olc clk output voltage low (3) 1.65 1.65 i ol =-2ma 90 mv r on switch on resistance (4) 1.65 1.65 v cmd, dat[3:0] =0v, i on =-2ma figure 5 10 ? ? r on delta on resistance (3, 5) 1.65 1.65 v cmd, dat[3:0] =0v, i on =- 2ma 0.85 ? power supply i cc(vddc) quiescent supply current (card) 1.95 0 v sw =0 or v ddc , i out =0 2 a i cc(vddh1/h2) quiescent supply current (hosts) 1.95 1.95 v sw =0 or v ddx, i out =0, v clki =v ddhx , v clko =open, oe=v ddc 2 a ? i host delta i cc(vddh1, vddh2) for one host powered off 1.95 1.95 / 0 0 / 1.95 v sw =0 or v ddx, i out =0, v clki =v ddhx , v clko =open, oe=v ddc 2 a notes: 3. guaranteed by characteriza tion, not production tested. 4. on resistance is determined by the voltage drop between the switch i/o pins at the indicated current through the switch. 5. ? r on =r on max ? r on min measured at identical v cc , temperature, and voltage.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fssd07 rev. 1.0.2 7 fssd07 ? 1-bit / 4-bit sd/sdio and mmc dual-host multiplexer dc electrical characteristics at 2.7v v ddc all typical values are for v ddc =2.7v at 25c unless otherwise specified. symbol parameter v ddc (v) v ddh1 / v ddh2 (v) conditions t a =-40 to +85c unit min. typ. max. common pins v ik clamp diode voltage 2.7 2.7 i ik =-18ma -1.2 v v ih control input voltage high 2.7 2.7 1.8 v il control input voltage low 2.7 2.7 0.8 i in s, oe input high current 3.6 3.6 v cntrl =0v to v ddc -1 1 a i oz off leakage current of all ports 3.6 3.6 v sw =0v to v ddc -1.0 0.5 1.0 a v ohc clk output voltage high (6) 2.7 2.7 i oh =-2ma 2.4 v v olc clk output voltage low (6) 3.6 3.6 i ol =-2ma 90 mv r on switch on resistance (7) 2.7 2.7 v cmd, dat[3:0] =0v, i on =-2ma figure 5 5.0 8.0 ? ? r on delta on resistance (6, 8) 2.7 2.7 v cmd, dat[3:0] =0v, i on =- 2ma 0.8 ? power supply i cc(vddc) quiescent supply current (card) 3.6 0 v sw =0 or v ddc , i out =0 2 a i cc (vddh1/c2) quiescent supply current (hosts) 3.6 3.6 v sw =0 or v ddx, i out =0, v clki =v ddhx , v clko =open, oe=v ddc 2 a ? i host delta i cc(vddh1, vddh2) for one card powered off 3.6 3.6 / 0 0 / 3.6 v sw =0 or v ddx, i out =0, v clki =v ddhx , v clko =open, oe=v ddc 2 a notes: 6. guaranteed by characteriza tion, not production tested. 7. on resistance is determined by the voltage drop between the switch i/o pins at the indicated current through the switch. 8. ? r on =r on max ? r on min measured at identical v cc , temperature, and voltage.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fssd07 rev. 1.0.2 8 fssd07 ? 1-bit / 4-bit sd/sdio and mmc dual-host multiplexer ac electrical characteristics at 1.8v v ddc all typical values are for v ddc =1.8v at 25c unless otherwise specified. symbol parameter v ddc (v) v ddh1 / v ddh2 (v) conditions t a =-40 to +85c unit min. typ. max. t on turn-on time, s, oe to cmd, dat[3:0] 1.65 to 1.95 1.65 to 3.6 v sw =0v, r l =1k ? , c l =20pf figure 7, figure 8 8 18 ns t off turn-off time, s, oe to cmd, dat[3:0] 1.65 to 1.95 1.65 to 3.6 v sw =0v, r l =1k ? , c l =20pf figure 7, figure 8 6 13 ns t rise1/ fall1 cmd/dat output edge rates (9) 1.65 to 1.95 1.65 to 3.6 r l =1k ? , c l =20pf (10-90%) figure 7, figure 8 3 ns t pd switch propagation delay (9) 1.65 to 1.95 1.65 to 3.6 r l =1k ? , c l =20pf figure 7, figure 89 4.5 9 ns t plh lh propagation delay 1clk, 2clk to clk 1.65 to 1.95 1.65 to 3.6 c l =20pf figure 10, figure 11 4 6 ns t phl hl propagation delay 1clk, 2clk to clk 1.65 to 1.95 1.65 to 3.6 c l =20pf figure 10, figure 11 4 6 ns t rise2/ fall2 clk output edge rates (9) 1.65 to 1.95 1.65 to 3.6 c l =20pf (10-90%) figure 7, figure 8 3 ns o irr off isolation (9) 1.8 1.65 to 3.6 f=10mhz, r t =50 ? , c l =20pf, figure 12 -60 db xtalk non-adjacent channel crosstalk (9) 1.8 1.65 to 3.6 f=10mhz, r t =50 ? , c l =20pf, figure 13 -60 db f toggle clock frequency (9) 1.8 1.65 to 3.6 c l =20pf 75 mhz note: 9. guaranteed by characteriza tion, not production tested.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fssd07 rev. 1.0.2 9 fssd07 ? 1-bit / 4-bit sd/sdio and mmc dual-host multiplexer ac electrical characteristics at 3.3v v ddc all typical values are for v ddc =3.3v at 25c unless otherwise specified. symbol parameter v ddc (v) v ddh1 / v ddh2 (v) conditions t a =-40 to +85c unit min. typ. max. t on turn-on time, s, oe to cmd, dat[3:0] 2.7 to 3.6 1.65 to 3.6 v sw =0v, r l =1k ? , c l =20pf figure 7, figure 8 8 18 ns t off turn-off time, s, oe to cmd, dat[3:0] 2.7 to 3.6 1.65 to 3.6 v sw =0v, r l =1k ? , c l =20pf figure 7, figure 8 6 13 ns t rise1/ fall1 cmd/dat output edge rates (10) 2.7 to 3.6 1.65 to 3.6 r l =1k ? , c l =20pf (10- 90%) figure 7, figure 8 3 ns t pd switch propagation delay (10) 2.7 to 3.6 1.65 to 3.6 r l =1k ? , c l =20pf figure 7, figure 8 2.5 6 ns t plh lh propagation delay 1clk, 2clk to clk 2.7 to 3.6 1.65 to 3.6 c l =20pf figure 10, figure 11 4 6 ns t phl hl propagation delay 1clk, 2clk to clk 2.7 to 3.6 1.65 to 3.6 c l =20pf figure 10, figure 11 4 6 ns t rise2/ fall2 clk output edge rates (10) 2.7 to 3.6 1.65 to 3.6 c l =20pf (10-90%) figure 7, figure 8 3 ns o irr off isolation (10) 2.7 1.65 to 3.6 f=10mhz, r t =50 ? , c l =20pf figure 12 -60 db xtalk non-adjacent channel crosstalk (10) 2.7 1.65 to 3.6 f=10mhz, r t =50 ? , c l =20pf, figure 13 -60 db f toggle clock frequency (10) 2.7 1.65 to 3.6 c l =20pf 75 mhz note: 10. guaranteed by characteriza tion, not production tested. capacitance symbol parameter v ddc (v) v ddh1/h2 (v) conditions t a =-40 to +85c unit min. typ. max. c in(s, oe, clk) control and nclk pin input capacitance (11) 0 2.7 v ddc =0v 2.5 pf c on common port on capacitance (11) (c dat[3:0], cmd ) 2.7 2.7 v oe =v ddc , v bias =0.5v, f=1mhz figure 14 7.5 pf c off input source off capacitance (11) 2.7 2.7 v oe =0v, v bias =0.5v, f=1mhz figure 15 4 pf note: 11. guaranteed by characteriza tion, not production tested.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fssd07 rev. 1.0.2 10 fssd07 ? 1-bit / 4-bit sd/sdio and mmc dual-host multiplexer test diagrams selec t ndat[3:0],ncmd dat[3:0],cmd v s = 0 or v ddh i on v on r on = v on /i on gnd v in gnd selec t dat[3:0],cmd v s i on v on gnd gnd v in gnd v in gnd gnd gnd select v s = 0 or v ddh nc a i oz v in gnd i oz v in gnd v in gnd gnd gnd each switch port tested separately. figure 5. on resistance figure 6. off leakage r l ,r s ,andc l are functions of the application environment (see ac tables for specific values). c l includes test fixture and stray capacitance. c l r l gnd gnd r s v s v sw gnd v out dat[3:0], cmd ndat[3:0],ncmd v ddx v v out v t rise = 2.5ns gnd v ddx 90% 90% 10% 10% t fall = 2.5ns v ddx /2 v ddx /2 input - v cntrl output - v out 50% v oh v ol t off t on +0.15v output - v out 50% v ol t on t off +0.15v v oh v ol v ol figure 7. ac test circuit load figure 8. turn on/off time waveforms t rise =2.5ns gnd v ddx 90% 90% 10% 10% t fall =2.5ns v ddx /2 v ddx /2 input - v sw output- v out 50% 50% v oh v ol t plh t phl rise t fall /2 v ddx /2 - - plh phl /2 - - figure 9. switch propagation delay (t pd ) waveform figure 10. ac test circuit load (clk) r l , r s and c l are function of application environment (see ac tables for specific values) c l includes test fixture and stray capacitance c l gnd gnd r s v s v clki gnd v out clk 1clk, 2clk r l , r s and c l are function of application environment (see ac tables for specific values) c l includes test fixture and stray capacitance c l gnd gnd gnd gnd r s r s v s v clki gnd v clki gnd gnd gnd v out v out clk 1clk, 2clk
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fssd07 rev. 1.0.2 11 fssd07 ? 1-bit / 4-bit sd/sdio and mmc dual-host multiplexer test diagrams (continued) t rise =2.5ns gnd v ddx 90% 90% 10% 10% t fall =2.5ns v ddx /2 v ddx /2 input - v clki output -v out 50% 50% v ohc v ol t plh t phl r s and r t are functions of the application environment (see ac tables for specific values). v out gnd gnd r t gnd gnd v s r s network analyzer r t gnd v s gnd off isolation = 20 log (v out /v in ) v in out r t gnd r t gnd gnd gnd gnd r s /v v in figure 11. clk propagation delay waveforms figure 12. channel off isolation v out gnd gnd r t gnd gnd v s r s network analyzer r t gnd r s and r t are functions of the application environment (see ac tables for specific values). v s gnd nc crosstalk = 20 log (v out /v in ) v in figure 13. channel-to-channel crosstalk v s = 0 or v ddh capacitance meter s f=1mhz ndat[3:0], ncmd, nclk v s = 0 orv ddh capacitance meter s f=1mhz ndat[3:0], ncmd, nclk ndat[3:0], ncmd, nclk figure 14. channel on capacitance figure 15. channel off capacitance
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fssd07 rev. 1.0.2 12 fssd07 ? 1-bit / 4-bit sd/sdio and mmc dual-host multiplexer physical dimensions figure 16. 24-lead, molded leadless package (mlp) package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . always visit fairchild semiconductor?s online packagi ng area for the most recent container drawings: http://www.fairchildsemi.com/packaging/mlp24b_tnr.pdf.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fssd07 rev. 1.0.2 13 fssd07 ? 1-bit / 4-bit sd/sdio and mmc dual-host multiplexer physical dimensions top view bottom view recommended land pattern 0.10 c 0.08 c b a c 0.10 c 2x 2x side view seating plane 0.10 c 0.05 0.00 7 13 1 0.10 cab 0.05 c 0.55 max. pin #1 ident 19 2.50 3.40 0.40 0.15 0.25 24x 0.45 0.55 0.35 0.45 23x 0.15 24 3.70 2.80 2.23 2.23 1 7 13 19 24 0.40 0.56 0.23 0.66 figure 17. 24-lead, ultra-thin molded leadless package (umlp), 0.4mm pitch package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . for current tape and reel specif ications, visit fairchild semi conductor?s online packaging area: http://www.fairchildsemi.com/packaging/micromlp24_tnr.pdf
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fssd07 rev. 1.0.2 14 fssd07 ? 1-bit / 4-bit sd/sdio and mmc dual-host multiplexer

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